1. Field of the Invention
The present invention relates generally to a method for forming a gate structure of a semiconductor device, and more particularly, the present invention relates to a method for fabricating a dual metal gate by using a damascene process.
2. Description of the Related Art
Recently, as development of semiconductor devices on the level of sub-0.1 micron has begun in earnest, a conventional gate electrode made of polysilicon or metal silicide has reached several physical limits.
For example, the polysilicon gate has problems, such as an increase in effective thickness of a gate insulating layer due to a gate depletion phenomenon, penetration of dopants from the p+ or n+ polysilicon gate to a substrate, and variation in the threshold voltage caused by a change of dopant distribution. In addition, the polysilicon gate is not suitable for realizing low resistance levels required for reductions in line width.
Thus, there has arisen a need for a new gate electrode with a new material or a new structure as an alternative to conventional gates. To meet such need, a metal gate electrode has been introduced and developed in the field. Since no dopant is basically required for the metal gate electrode, the above-noted problems existing in conventional gates are solved naturally.
Furthermore, the conventional metal gate electrode permits formation of a single metal gate in which a threshold voltage is symmetrically formed in the NMOS and PMOS regions by using metal with a value of the work function at an intermediate band gap of silicon. The metal gate electrode may be made of various metal, such as W, WN, Ti, TiN, Mo, MoN, Ta, TaN, Ti3Al and Ti3AlN.
Unfortunately, when a single metal gate is employed for a CMOSFET device, a flat band voltage is decreased in the NMOS and PMOS regions and consequently, the threshold voltage is increased. In order to reduce the threshold voltage, a buried channel is formed through counter doping. However, this gives rise to increases of a short channel effect and a leakage current in the CMOSFET device.
Accordingly, a new attempt to form a dual metal gate has been made by separately using different kinds of metal gates with different values of the work function in the respective NMOS and PMOS regions, based upon the operational principle of an existing dual polysilicon gate.
FIGS. 1A to 1E show the steps of a method for fabricating a conventional dual metal gate of the semiconductor device according to the prior art.
Referring to FIG. 1A, after a field oxide layer 2 is formed on a semiconductor substrate 1, an NMOS region 3a and a PMOS region 3b are separately formed in the semiconductor substrate 1 by using masking and ion-implanting processes well known in the art. Next, a thin screen oxide layer (not shown) is formed on the semiconductor substrate 1, and proper ions for adjusting a threshold voltage are implanted respectively into the NMOS and PMOS regions 3a and 3b by a photo masking process.
Then, after the screen oxide layer is removed, as shown in FIG. 1B, a gate insulating layer 4, a metal layer 5 for NMOS and a barrier metal layer 6 are sequentially formed over the entire semiconductor substrate 1. The metal layer 5, used for NMOS, comprises a metal having a Fermi energy near a conduction band of silicon.
Next, an appropriate first etch mask (not shown) is formed on the NMOS region 3a. Then, referring to FIG. 1C, the barrier metal layer 6 and the NMOS metal layer 5 are removed in sequence from the PMOS region 3b by a photo etching process using the first etch mask.
Thereafter, as shown in FIG. 1D, a metal layer 7, used for PMOS, is deposited over the entire resultant structure on the semiconductor substrate 1.
Then, an appropriate second etch mask (not shown) is formed on the PMOS metal layer 7. Next, referring to FIG. 1E, dual metal gates 8a and 8b are separately formed in the NMOS and PMOS regions 3a and 3b by a photo etching process using the second etch mask.
Subsequently, a spacer nitride is deposited over an entire resultant structure and then subjected to a blanket etching process. Therefore, a spacer 9 is formed on the lateral sidewalls of the dual metal gates 8a and 8b. Next, a source/drain region 10a and 10b is formed in each of the NMOS and PMOS regions 3a and 3b by a source/drain ion implantation process, so that fabrication of a CMOSFET device having dual metal gates is completed.
Unfortunately, the above-described conventional dual metal gate structure has several disadvantages. For example, when the NMOS and PMOS metal layers are patterned to form the metal gate, it is difficult to institute an etch recipe for the metal gate. Additionally, an etching process or an ion implantation process may create plasma damage, and a thermal process performed after formation of the metal gate may create thermal damage.
Furthermore, since the metal gate of the NMOS region is different from that of the PMOS region in height and material thereof, it is hard to reliably establish the etching process capable of preventing the semiconductor substrate from being damaged.
It is therefore an object of the present invention to provide an improved method for fabricating a dual metal gate structure for a semiconductor device while allowing simplified, stable and reliable process.
It is another object of the present invention to provide an improved method for fabricating a dual metal gate structure for a semiconductor device while minimizing damage of the gate caused by plasma or thermal ambience and thereby enhancing the profile and operating characteristics of the gate.
It is still another object of the present invention to provide an improved method for fabricating a dual metal gate structure for a semiconductor device while attaining a high degree of integration of the device.
These and other objects in accordance with the present invention are attained by a method using a damascene process to form a dual metal gate structure.
The method according to the present invention comprises providing a semiconductor substrate having a PMOS region and an NMOS region formed therein, and sequentially depositing a first gate insulating layer and a first metal layer over the semiconductor substrate. The first metal layer and the first gate insulating layer are then sequentially patterned, so that a first gate is formed in a first region, the first region being selected between either the PMOS region and the NMOS region, and a dummy gate is formed in the second region not selected as the first region. Next, a spacer is formed on each lateral sidewall of the first gate and the dummy gate, and a source/drain region is formed in the semiconductor substrate adjacent each side of the first gate and the dummy gate. Thereafter, an interlayer dielectric layer is deposited on the resultant structure, including over the source/drain region, and polished so as to expose the patterned first metal layer. The dummy gate is then removed so as to expose a portion of the semiconductor substrate in the second region. Next, a second gate insulating layer and a second metal layer are sequentially deposited on the exposed portion of the semiconductor substrate and the interlayer dielectric layer. Subsequently, the second metal layer and the second gate insulating layer are polished so as to expose the interlayer dielectric layer. Thereby, a second gate is established in the second region.
In the method, first and second metal layers may be used for NMOS and PMOS, respectively. The first metal layer for NMOS is preferably made of a metal having a work function value of 4.2 eV or less, while the second metal layer used for PMOS is preferably made of a metal having a work function value of 4.8 eV or greater. Alternatively, the first and second metal layers may be used for PMOS and NMOS, respectively, so that the definition of the first and second regions are reversed. In this case, the second metal layer for NMOS is preferably made of a metal having a work function value of 4.2 eV or less, and the first metal layer for PMOS is preferably made of metal having a work functional value of 4.8 eV or more.
According to an alternate embodiment of the present invention, another method for fabricating a dual metal gate structure for a semiconductor device is described. The alternate embodiment method comprises providing a semiconductor substrate having a PMOS region and an NMOS region formed therein, and sequentially depositing a first gate insulating layer, a first metal layer and a first mask layer on the semiconductor substrate. Next, after the first mask layer is patterned, the first metal layer and the first gate insulating layer are sequentially etched by using the patterned first mask layer as an etch barrier, so that a gate structure is formed respectively in the PMOS region and the NMOS region. A spacer is then formed on a lateral sidewall of the gate structure, and a source/drain region is formed in the semiconductor substrate adjacent appropriate sides of the gate structure. Thereafter, an interlayer dielectric layer is deposited on the resultant structure having the source/drain region, and this is polished together with the first mask layer so as to expose the etched first metal layer. Next, a second mask layer is partially deposited on the resultant structure so as to cover the exposed first metal layer in one region selected from either the PMOS region or the NMOS region, thereby defining a first region. The first metal layer and the first gate insulating layer are then sequentially etched by using the second mask layer as an etch barrier, so that a portion of the semiconductor substrate is exposed in the region not selected in the previous steps thereby defining a second region. A second gate insulating layer and a second metal layer are sequentially deposited over the exposed portion of the second region of the semiconductor substrate, the interlayer dielectric layer, and the second mask layer. Subsequently, the second metal layer, the second gate insulating layer, and the second mask layer are polished so as to expose the interlayer dielectric layer, thereby, completing formation of the dual gate structure.
Preferably, the first metal layer may be deposited with a thickness of between, 1000 and 3000 xc3x85. The first and second metal layers may be used for NMOS and PMOS, so that the NMOS is defined as the first region and the PMOS is defined as the second region or alternatively for PMOS and NMOS, respectively, so that the definitions of the first and second regions are reversed. The metal layer for NMOS is preferably made of a metal having a work function value of 4.2 eV or less, while the metal layer for PMOS is preferably made of a metal having a work function value of 4.8 eV or greater.
In addition, the first gate insulating layer and the second insulating layer may be respectively made of a material selected from a group comprising oxide, oxy-nitride, and other materials having a high dielectric constant. Furthermore, the first mask layer and the second mask layer may be deposited respectively to a thickness of between 800 and 1000 xc3x85, and the interlayer dielectric layer may be deposited to a thickness of between 4000 and 6000 xc3x85. Etching of the first metal layer and the first gate insulating layer may be performed by a dry etch or a wet etch.